2021 Theses Doctoral
Integrated and Distributed Digital Low-Drop-Out Regulators with Event-Driven Controls and Side-Channel Attack Resistance
Kim, Sung Justin
A modern system-on-chip (SoC) integrates a range of analog, digital, and mixed-signal building blocks, each with a dedicated voltage domain to maximize energy efficiency. On-chip low-drop-out regulators (LDOs) are widely used to implement these voltage domains due to their advantages of high power density and the ease of integration to a complementary metal-oxide-semiconductor (CMOS) process. Recently, digital LDOs have gained large attention for their low input voltage support for emerging sub-mW SoCs, portability across designs, and process scalability. However, some of the major drawbacks of a conventional digital LDO design are (i) the trade-off between control loop latency and power dissipation which demands a large output capacitor, (ii) failure to address the performance degradations caused by the parasitics in a practical power grid, and (iii) insufficient power-supply-rejection-ratio (PSRR) and large ripple in the output voltage. Chapters 2 through 4 of this thesis present my research on the design and circuit techniques for improving the aforementioned challenges in fully-integrated digital LDOs. The first work implements a hybrid event- and time-driven control in the digital LDO architecture to improve the response and settling time-related metrics over the existing designs. The second work presents a power delivery system consisting of 9 distributed event-driven digital LDOs for supporting a spatially large digital load. The proposed distributed LDO design achieves large improvements in the steady-state and non-steady-state performances compared to a single LDO design. In the third work, we prototype a digital LDO based on new current-source power-FETs to achieve a high PSRR and low output voltage ripple. Lastly, on-chip voltage regulators have recently found usefulness in hardware security applications. An on-chip LDO can be used to improve the side-channel attack (SCA) resistance of a cryptographic core with design modifications to the classical LDO architecture. However, the existing designs incur non-negligible overheads in performance, power, and silicon area due to the conventional active-for-all-encryption-rounds architecture. In the last chapter, we propose a detection-driven activation technique to achieve a near-zero energy-delay-product (EDP) overhead in a SCA resilient digital LDO. In this architecture, the LDO can detect an attack attempt and enable SCA protection only if an attack is detected.
- Electrical engineering
- Voltage regulators--Research
- Digital integrated circuits--Design and construction
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Design of Low Voltage LDO Voltage Regulator for Battery Operated Wireless Sensor Nodes
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- Piyushkumar M. Chaniyara ORCID: orcid.org/0000-0001-9595-9262 7
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This paper presents the low voltage low dropout voltage regulator for battery operated wireless sensor nodes. The gain boosted folded cascode operational amplifier presented here is use as an error amplifier with improved gain (80.16 dB). For low power operation and low quiescent current (1.2 uA) error amplifier is operated in sub threshold region. The voltage regulator presented here is inherently stable without any external RC compensation network with 30 nF as load capacitor. The proposed voltage regulator has line regulation of 0.031% with good power supply rejection ratio (PSRR) −60 dB at 1.5 kHz and −40 dB at 1 GHz. All the simulation results are carried out in CMOS 90 nm technology using cadence virtuoso tool.
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Chaniyara, P.M. (2021). Design of Low Voltage LDO Voltage Regulator for Battery Operated Wireless Sensor Nodes. In: Arunachalam, V., Sivasankaran, K. (eds) Microelectronic Devices, Circuits and Systems. ICMDCS 2021. Communications in Computer and Information Science, vol 1392. Springer, Singapore. https://doi.org/10.1007/978-981-16-5048-2_19
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IMAGES
VIDEO
COMMENTS
The Design of An LDO Regulator Many mixed-signal systems incorpo-rate LDO regulators to generate local supply voltages for various building blocks. LDOs isolate the circuits from one another's noise and from the noise on the global supply, V DD. For optimum performance, the design of each LDO is tailored to the particu-lar cell that it feeds.
Amongst all the design metrics of LDO, a fast load transient response with small ... This thesis also analyzes its design robustness in terms of stability and offset. A low-cost trim method is also introduced to achieve a high yield for potential production. This LDO with high swing dynamic
1 1 INTRODUCTION The Low-dropout (LDO) voltage regulator is an integral part of SoC designs as they are lightweight and a source of cleaner power compared to switching regulators and
I. Introduction 1.1 Definition. A series low-drop-out regulator is a circuit that provides a well-specified and stable dc voltage [1] whose input to output voltage difference is low [2]. The drop-out voltage is defined as the value of the input/output differential voltage where the control loop stops regulating.
This thesis presents my research on fully-integrated digital LDO designs based on event-driven control architecture. My research focuses on scaling down the output capacitor size (C OUT) to the integrable level and improving transient performance such as maximum voltage change and settling time.
This thesis demonstrates a 1.6GHz supply-regulated PLL design using active Butterworth low pass filter and high power supply rejection ratio LDO regulator in 110nm standard CMOS technology with 1.0V power supply. The regulator output is 0.8V which supplies to all the PLL blocks.
Low Dropout Voltage Regulator (LDO) The LDO act as a variable resistor that is placed between input power source and the load in order to drop and control the voltage applied to the load. Compared to DC‐DC switching regulators, LDOs are: Of continuous operation. Easier to use.
Chapters 2 through 4 of this thesis present my research on the design and circuit techniques for improving the aforementioned challenges in fully-integrated digital LDOs. The first work implements a hybrid event- and time-driven control in the digital LDO architecture to improve the response and settling time-related metrics over the existing ...
Design of a low voltage,low drop-out (LDO) voltage cmos regulator. Chaithra T S Ashwini. Engineering. 2012. In this paper a low voltage, low drop-out (LDO) voltage regulator design procedure is proposed and implemented using 0.25 micron CMOS process. It discusses a 3 to 5V, 50mA CMOS low drop-out linear…. Expand.
This thesis also analyzes its design robustness in terms of stability and offset. A low-cost trim method is also introduced to achieve a high yield for potential production. This LDO with high swing dynamic biasing impedance-attenuation buffer has been fabricated in 0.18-μm HV CMOS process. The silicon size of the LDO is 137000 μm2.
Figure 1 depicts the proposed LDO circuit, it presents a range of performance advantages that make it an excellent choice for low-power and high-precision applications. One of its main features is the use of sub-threshold MOS transistors in the feedback network, which significantly reduces power consumption and allows for a smaller silicon area, making it ideal for integration into the SoCs.
The small signal model of proposed LDO is shown in Fig. 2. In this figure, the LDO uses the multi-stage current amplifier and a small capacitor compensation Cm inside the system. That makes the system stable. CF is the output parasitic capacitance, generally is 10 pF to 100 pF. Fig. 3. The proposed schematic of LDO.
Prof. Gabriel Alfonso Rincón-Mora, Ph.D.
The Low Dropout Regulator. low-dropout (LDO) regulator is an essential power management circuit in today's systems on chip (SOCs). Much to grammarians' chagrin, the noun regulator has been dropped, and the circuit is simply called the LDO. The need for supply voltage regula-tion, of course, goes back many de-cades.
LDO. We can also design an ultra-low quiescent current low-dropout regulator with small output voltage variation and improved load regulation. References Tiikkainen M, "LDO Voltage Regulator for On-Chip Power Management," University of Oulu, Department of Electrical Engineering. Master's Thesis, 86p. 2014.
MS thesis, National Cheng Kung University, January 2008. Google Scholar ... Design of Low Voltage LDO Voltage Regulator for Battery Operated Wireless Sensor Nodes. In: Arunachalam, V., Sivasankaran, K. (eds) Microelectronic Devices, Circuits and Systems. ICMDCS 2021. Communications in Computer and Information Science, vol 1392.
The Design of An LDO Regulator. Gareeb Nawaz Chhagan Charan. National Institute of Technology, Kurukshetra National Institute of Technology, Haryana, India Kurukshetra, Haryana, India. 32219230 ...
<P>Low dropout (LDO) regulators are widely used in portable electronic devices because they occupy small chip and printed circuit board (PCB) areas. These regulators are appropriate for low-power applications because of heat dissipation. This chapter first introduces the basic LDO regulator, and then, presents concerns over compensation for loop stability to develop dominant pole compensation ...
Systems-on-Chip's (SoC) design complexity demands a high-performance linear regulator architecture to maintain a stable operation for the efficient power management of today's devices. Over the decades, the low-dropout (LDO) voltage regulator design has gained attention due to its design scalability with better performance in various application domains. Industry professionals as well as ...
This paper presents an ultra-low noise low-dropout (LDO) regulators for powering RF applications. The proposed LDO employs two internal noise reduction network at the output of the bandgap reference (BGR), and between output and feedback resistors node (VFB in Fig. 1) of LDO to achieve ultra-low noise at interest frequencies. The 5-bits controlled resistor ladder is adopted to compensate the ...
A low dropout regulator (LDO) with ultra low output noise is described. The proposed structure of LDO with internal noise filter is discussed and related design problems along with their possible solutions are highlighted. The LDO ensures output noise below 1OmuV (10Hz to 100kHz) having quiescent current about 25muA for no load. Maximum output current of 100mA is available. The LDO is stable ...
Nanyang Technological University
Many mixed-signal systems incorporate LDO regulators to generate local supply voltages for various building blocks. LDOs isolate the circuits from one another's noise and from the noise on the global supply, <inline-formula><tex-math notation="LaTeX">${V}_{\\text{DD}}$</tex-math></inline-formula> . For optimum performance, the design of each LDO is tailored to the particular cell that it ...
A Low-drop-out (LDO) regulator is a DC linear voltage regulator which can operate with a very small input-output differential voltage. The demand for the low-voltage, low drop out (LDO) regulators is increasing because of the growing demand of portable electronics, i.e., mobile phones, pagers, laptops, etc as well as industrial and automotive ...